#-----------------------------------------------------------
# Vivado v2023.1 (64-bit)
# SW Build 3865809 on Sun May  7 15:05:29 MDT 2023
# IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Thu Jun  8 10:53:05 2023
# Process ID: 508
# Current directory: C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/synth_1
# Command line: vivado.exe -log basys3top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source basys3top.tcl
# Log file: C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/synth_1/basys3top.vds
# Journal file: C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/synth_1\vivado.jou
# Running On: DESKTOP-5QEHRRG, OS: Windows, CPU Frequency: 3693 MHz, CPU Physical cores: 12, Host memory: 34281 MB
#-----------------------------------------------------------
source basys3top.tcl -notrace
Command: read_checkpoint -auto_incremental -incremental C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/utils_1/imports/synth_1/basys3top.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/utils_1/imports/synth_1/basys3top.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top basys3top -part xc7a35tcpg236-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 3452
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Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1253.184 ; gain = 411.832
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INFO: [Synth 8-638] synthesizing module 'basys3top' [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/basys3top.vhd:40]
INFO: [Synth 8-3491] module 'seven_seg' declared at 'C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/seven_seg.vhd:34' bound to instance 'sseg' of component 'seven_seg' [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/basys3top.vhd:44]
INFO: [Synth 8-638] synthesizing module 'seven_seg' [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/seven_seg.vhd:41]
INFO: [Synth 8-256] done synthesizing module 'seven_seg' (0#1) [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/seven_seg.vhd:41]
INFO: [Synth 8-256] done synthesizing module 'basys3top' (0#1) [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/basys3top.vhd:40]
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Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1343.922 ; gain = 502.570
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1343.922 ; gain = 502.570
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1343.922 ; gain = 502.570
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1343.922 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/constrs_1/new/basys3.xdc]
Finished Parsing XDC File [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/constrs_1/new/basys3.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/constrs_1/new/basys3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/basys3top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/basys3top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.855 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1436.855 ; gain = 0.000
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
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Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Loading Part and Timing Information
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Loading part: xc7a35tcpg236-1
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Applying 'set_property' XDC Constraints
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start RTL Component Statistics 
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Detailed RTL Component Info : 
+---Muxes : 
	   5 Input    4 Bit        Muxes := 2     
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Finished RTL Component Statistics 
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Start Part Resource Summary
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Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
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Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Start Writing Synthesis Report
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Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-------+------+
|      |Cell   |Count |
+------+-------+------+
|1     |BUFG   |     1|
|2     |CARRY4 |     4|
|3     |LUT1   |     3|
|4     |LUT3   |     6|
|5     |FDRE   |    13|
|6     |IBUF   |     1|
|7     |OBUF   |    12|
+------+-------+------+
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
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Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1436.855 ; gain = 502.570
Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.855 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.855 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Synth Design complete | Checksum: 4dde06ef
INFO: [Common 17-83] Releasing license: Synthesis
26 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.855 ; gain = 974.078
INFO: [Common 17-1381] The checkpoint 'C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/synth_1/basys3top.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file basys3top_utilization_synth.rpt -pb basys3top_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Thu Jun  8 10:53:38 2023...
